Priority is claimed to Japanese Patent Application Number JP 2005-224606 filed on Aug. 2, 2005, the disclosure of which is incorporated herein by reference in its entirety.
1. Field of the Invention
The present invention relates to an insulated gate semiconductor device and a manufacturing method thereof. More particularly, the present invention relates to an insulated gate semiconductor device which reduces an ON-resistance of the device, and which corrects a failure in wire bonding, and a manufacturing method thereof.
2. Description of the Related Art
FIGS. 9A and 9B show a conventional semiconductor device. FIG. 9A is a cross-sectional view and FIG. 9B is a plan view. FIG. 9A is a cross-sectional view taken along the line b-b in FIG. 9B.
As shown in FIG. 9A, an element region 51 is provided with, for example, a MOSFET 52 having a trench structure. Specifically, a drain region is formed with providing an n− type epitaxial layer on an n+ type silicon semiconductor substrate 31, and a p type channel layer 34 is provided thereon. Thereafter, a trench 37, which penetrates the channel layer 34 to reach the drain region 32, is formed, and an inner wall of the trench 37 is covered with a gate oxide film 41. Thus, a gate electrode 43, which is made of polysilicon buried in the trench 37, is provided. In a surface of the channel layer 34 adjacent to the trench 37, an n+ type source region 45 is formed. Moreover, in the surface of the channel layer 34 between the source regions 45 respectively of each two adjacent cells, a p+ type body region 44 is provided. The gate electrode 43 is covered with an interlayer insulating film 46. On the interlayer insulating film 46, a metal electrode layer 47, which is connected to the element region 51, is provided.
As shown in FIG. 9B, the metal electrode layer 47 is patterned into a predetermined shape, and forms a source electrode 47s, which covers the entire surface of the element region 51, a gate pad electrode 47g, and the like. The source electrode 47s is in contact with the source region 45 and the body region 44. Moreover, the gate pad electrode 47g is connected to the gate electrode 43 in the element region 51 through a protection diode D or the like.
On the metal electrode layer 47, a nitride film 50, which serves as a protective film, is provided. An opening is provided in the nitride film 50 and a bonding wire 60 is fixed therein. This technology is described for instance in Japanese Patent Application Publication No. 2002-368218.
The bonding wires 60 are fixed, for example, at four spots on the source electrode 47s covering the element region 51, and at one spot on the gate pad electrode 47g. 
In an insulated gate semiconductor device such as a MOSFET, reduction in an ON-resistance has been an important factor for improving characteristics of the insulated gate semiconductor device. Various methods are adopted for the reduction in the ON-resistance. For example, a resistance value of the metal electrode layer 47 (the source electrode 47s), which is in contact with the entire surface of the element region, is easily reduced at relatively low costs. To be more specific, the metal electrode layer 47 made of aluminum alloy is generally adopted as a metal layer having a low resistance value.
However, in the case of the metal electrode layer 47 made of aluminum alloy, when thin gold (Au) wires are used as bonding wires, there is a problem that a failure occurs after a certain period of time passes, for example. Specifically, when an Au ball is fixed directly to the metal electrode layer 47, Au and Al are mutually diffused in an interface therebetween as time passes. Thus, an Au/Al eutectic layer is formed. The Au/Al eutectic causes volume expansion, and stress generated at the time of the volume expansion applies pressure to the interlayer insulating film 46.
When the pressure is applied to the interlayer insulating film 46, cracks C are generated (see FIG. 9A). Accordingly, there is a problem that a leak occurs between a gate and a source.
Moreover, when further reduction in the ON-resistance is sought, for example, it is also conceivable that a metal layer having a lower resistance value is adopted instead of the aluminum alloy layer. If the metal layer is not the aluminum alloy layer, occurrence of the cracks C due to the Al/Au eutectic described above can be avoided. However, an existing sputtering apparatus can be utilized for the aluminum alloy layer, and the layer is formed at low costs. Moreover, the aluminum alloy layer is easily patterned, and is suitable as the metal electrode layer 47. Therefore, the resistance value can be further reduced by adopting the aluminum alloy as the metal electrode layer 47, and by increasing a thickness of the metal electrode layer 47.
However, there is a limitation on an increase in the thickness of the aluminum alloy. Specifically, in a case where the aluminum alloy is patterned by low-cost wet etching, side etching takes place for an amount equivalent to that of etching in a depth direction. Thus, the larger the thickness of the aluminum alloy is, the longer distance between adjacent patterns (for example, the gate pad electrode 47g and the source electrode 47s) needs to be secured. As a result, pattern arrangement including the element region 51 and the gate pad electrode 47g increases in area more than necessary. Thus, there is a problem that a chip size is increased.
Meanwhile, if dry etching is adopted, no side etching takes place. However, an etching apparatus is expensive. Moreover, an etching selection ratio of a resist film as an etching mask to the aluminum alloy imposes a limit on a thickness which can be etched. Specifically, a dry etcher of the aluminum alloy has a low selection ratio of the resist film to the aluminum alloy. Thus, the resist film, which should be left, is etched while etching the thick aluminum alloy. Hence, a mask pattern cannot be accurately formed. Although the resist film may be formed to have a large thickness, a resolution is deteriorated in that case. For this reason, the thick resist film is not suitable for a minute pattern.